Job Title: Lead ASIC Design Engineer - Synthesis, STA, Prime Time
Job Location: San Jose, CA
Compensation: $160K - $240K base Depending on experience plus stock options!
Requirements: ASIC Design, Front to Back Design, Synthesis, Prime Time, STA, Lint, CDC, LEC
We were founded in 2020 by a team of veterans in Silicon Valley, and our mission is to accelerate AI computing in data centers and HPC by introducing high-performance, power efficient, scalable and cost-effective interconnect solutions. AI computing and data center architectures are undergoing a fundamental transformation of disaggregation and composability, driven by the enablement of CXL (Computing Express Link) technology.
We are working on the world's leading edge PCIe & CXL switch and we're now looking to hire an ASIC front-to-back design sysnthesis lead.
Top Reasons to Work with Us
1) Competitive Compensation ($180K - $240K base Depending on Experience)
2) Comprehensive Benefits package including stock options!
3) The chance to join a small start-up tackling challenging problems with huge upside potential!
What You Will Be Doing
As an ASIC front to back design lead, you will lead the establishing & maintaining Synthesis, STA, Equivalency flows. You will be working with the ASIC design engineers to ensure high quality RTL, design constraints & Netlist preparation to hand off to a third-party physical design company. You will be responsible for ensuring the physical design partner receives Netlist & assist them with the design constraints issues as well as overseeing the floor planning, place & route & CDC placements. Once the Place & Route is complete, you will receive the post-layout Netlist to resolve the timing closure issues. PCIe/CXL switch chips have a high gate count & require a deep understanding of hierarchical Synthesis. Reponsibilities include:
- Build flows for methodologies incorporating front to back flow for Lint, Synthesis, prime time timing analysis, CDC & equivalency check.
- Writing scripts & establishing automation for Synthesis & Prime time tools.
- Provide support for ASIC tools and flows
- Work with 3rd party vendor with the Netlist hand-off & oversee the physical design & ensure a clean tape out.
- Full chip & block level timing constraints ensuring area & timing optimization
- Implement functional ECOs
- Monitoring DFT insertion for scan, memory Bist & Loopback tests mechanisms.
What You Need for this Position
Must have a Bachelor's (Master's or Ph.D. preferred) in Computer Science, Electrical Engineering, Computer Engineering, or similar with 10 - 15+ years of experience:
- 10 - 15 years of experience in chip development & familiaritiy with ASIC CAD & EDA tools
- Knowledge with Synopsys synthesis & STA tools.
- Experience with high gate count ASICs
- Experience with ASIC methodologies such as Verilog design, Lint, Synthesis, STA & DFT.
- Strong track record of hierarchical synthesis, STA, Lint, CDC & LEC methodologies,
- Strong experience in design constraints
- Solid experience in Hierarchical Synthesis & Static timing analysis.
- Proficiency in Perl scripting for automation.
So, if you are a Principal ASIC Design Engineer with strong front to backend synthesis experience, please apply today! or send an updated copy of your resume to Mike.Vandenbergh@CyberCoders.com for immediate consideration!
Benefits
- Medical/Dental/Vision
- PTO/Vacation Days
- Equity
Applicants must be authorized to work in the U.S.
Email me to apply for this position
